Project X-Ray
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Xilinx 7-series Architecture
Overview
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Bitstream format
Interconnect
PIPs
Distributed RAMs (DRAM / SLICEM)
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Index
A
|
B
|
C
|
D
|
F
|
H
|
I
|
L
|
M
|
N
|
P
|
R
|
S
|
T
|
W
A
ASIC
B
basic element
basic logic element
BEL
Bitstream
BLE
Block RAM
C
CFA
CLB
Clock
Clock backbone
Clock domain
Clock region
Clock spine
Column
Configurable logic block
D
Database
F
Fabric sub region
FF
Flip flop
FPGA
Frame
Frame base address
FSR
Fuzzer
H
Half
HDL
Horizontal clock row
HROW
I
I/O block
INT
Interconnect tile
L
LUT
M
MUX
N
Node
P
PIP
Place and route
PnR
Programmable interconnect point
R
Region of interest
ROI
Routing fabric
S
Segment
Site
Slice
Specimen
T
Tile
W
Wire
Word
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