Welcome to Project X-RayΒΆ
Project X-Ray documents the Xilinx 7-Series FPGA architecture to enable development of open-source tools. Our goal is to provide sufficient information to develop a free and open Verilog to bitstream toolchain for these devices.
- Project X-Ray
- Quickstart Guide
- C++ Development
- Process
- Database
- Current Focus
- Contributing
- Contributing to Project X-Ray
- Fuzzers
- Minitests
- CLB_BUSED Minitest
- clb-carry_cin_cyinit Minitest
- clb-configs Minitest
- CLB_MUXF8 Minitest
- clkbuf Minitest
- eccbits Minitest
- FIXEDPNR Minitest
- LiteX minitest
- lvb_long_mux Minitest
- nodes_wires_list Minitest
- FASM Proof of Concept using Vivado Partial Reconfig flow
- Usage
- Using Vivado to generate .fasm
- PICORV32-v Minitest
- PICORV32-y Minitest
- pip-switchboxes Minitest
- ROI_HARNESS Minitest
- Quickstart
- How it works
- Minitests for SRLs
- tiles_wires_pips Minitest
- Timing minitest
- Model quality
- Running the model
- util Minitest
- Tools